Electronic systems, such as communication systems may include multiple clocks that are used, for example, to sample signals for processing during signal transmission and reception. Often the clocks are not synchronized, which may result in sampling errors, such as too many or too few samples in the received signal. For example, in an interface to an ISDN line having an external clock, or in a PCM interface toward a telephone system that extracts samples at its own rate, different clock domains may interact, and these clock domains may not be synchronized.
To correct for these sampling errors, a new sample may be inserted into the signal to compensate for a sample that arrives late, or a sample may be deleted from the signal to compensate for samples that arrive too early. For example, samples may be input to a first-in-first-out buffer (FIFO). If the FIFO is almost full, a sample may be removed. If the FIFO is almost empty, a sample may be inserted. A disadvantage of these corrections is that an audible distortion or noise may be created by adding or removing the samples to or from a speech signal.